The present invention generally relates to the field of non-volatile memories based on phase-change materials, also known in the art as ovonic unified memories.
Ovonic unified or phase-change memories are an emerging type of electrically-alterable non-volatile semiconductor memories. These memories exploit the properties of materials (phase-change materials) that can be reversibly switched between an amorphous phase and a crystalline phase when heated. A phase-change material exhibits different electrical characteristics, particularly a different resistivity, peculiar to each one of the two phases; thus, each material phase can be conventionally associated with a corresponding one of the two logic values, “1” and “0”.
Typically, the memory includes a matrix of phase-change memory cells, arranged in rows and columns with associated word lines and bit lines, respectively. Each memory cell consists of a storage element usually connected in series to an access element; each memory cell is connected between the respective word line and the respective bit line.
The memory cells can be selected for a reading operation, for example, by applying suitable voltages to the respective word lines and suitable current pulses to the respective bit lines. A voltage reached at the bit line depends on the resistance of the storage element, i.e., on the logic value stored in the selected memory cell.
The logic value stored in the memory cell is evaluated by sense amplifiers of the memory. Typically, a sense amplifier includes a comparator receiving the bit line voltage, or a related voltage, and a suitable reference voltage. In the case in which the bit line voltage is higher than the reference voltage, this situation, for example, is decreed to correspond to a stored logic value “0”, whereas in the case in which the bit line voltage is smaller than the reference voltage, this situation is decreed to correspond to the stored logic value “1”.
While the access element can consist of a select transistor or diode, the threshold switch may be made of a phase-change material, similarly to the storage element serially connected thereto. This element switches (without changing its phase) from a high-resistance condition to a low-resistance condition when a voltage applied thereacross exceeds a threshold value and reverts to the high-resistance condition when a current flowing therethrough falls below a minimum holding value. A voltage across the access element in the low-resistance condition has a substantially constant value (holding voltage), such as about 1 V, in series with a dynamic resistance dV/dI, such as about 200 ohms. In this case, the matrix of memory cells can be advantageously provided without any transistor, and then using a single technological thin film process.
During a reading operation, the read current pulse causes the charging (or discharging, depending on polarity selected by the designer) of stray capacitance intrinsically associated with the bit line, and, accordingly, a corresponding transient of the bit line voltage at each selected bit line. The respective bit line voltage raises towards a corresponding steady value, Vfinal, depending on the logic value stored in the selected memory cell.
The transient of the bit line voltage depends not only on the stray capacitances associated with the bit lines, but also on operative parameters of the storage-elements and of the access elements, such as impedance and threshold/holding voltages. Accordingly, it may be difficult to design robust sense amplifiers for high margin reading of memories based on a phase-change material because of a large variability in those operative parameters of the storage elements and of the access elements, since parameters also vary with temperature. A problem is that such a variability usually involves a reduction in a discrimination margin between the reference voltage and a value of the bit line voltage to be compared thereto.
Furthermore, a variability in the threshold voltage of the access element brings to an uncertainty on a time in which the access element is switched on and then on a time in which the bit line voltage reaches a steady-state value to be sensed. Accordingly, such a variability has to be taken into account for the timing of a reading operation. Inevitably, the reading operation is slowed down, since the timing has to be based on the worst cases.